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PRELIMINARY
CY7B9331
HOTLinkTM OLC Receiver
Features
Fibre Channel compliant IBM ESCONTM compliant OLC Compatible system interface 8B/10B-coded or 10-bit unencoded 160- to 330-Mbps data rate No external PLL components Dual ECL 100K serial inputs Low power: 650 mW Compatible with fiberoptic modules, coaxial cable, and twisted pair media * Built-In Self-Test * 28-pin SOIC/PLCC * * * * * * * * * 330 Mbits/second. The HOTLink OLC Receiver system interface has been tailored to match OLC (Optical Link Card) timing and functionality. The HOTLink receiver accepts the serial bit stream at its differential line receiver inputs and, using a completely integrated PLL clock synchronizer, recovers the timing information necessary for data reconstruction. The bit stream is deserialized, decoded, and checked for transmission errors. The recovered byte is presented in parallel to the receiving host along with a byte rate clock. The 8B/10B encoder/decoder can be disabled in systems that already encode or scramble the transmitted data. A Built-In Self-Test pattern generator and checker allows testing of the transmitter, receiver, and the connecting link as a part of a system diagnostic check. The CY7B9331 HOTLink Receiver is a companion part to the CY7B923 HOTLink Transmitter. The HOTLink chip set provides a complete physical interface solution. For further information on HOTLink Transceiver and Receiver functions see the CY7B923/933 datasheet.
Functional Description
The CY7B9331 HOTLink OLC Receiver is a point-to-point communications building block that receives data over high-speed serial links (fiber, coax, and twisted pair) at 160 to
Receiver Logic Block Diagram
Pin Configurations
SOIC Top View
INA- INA+ LOOP BISTEN ENSYNC GND SYNC GND VCCN RVS (Q j ) (Q h) Q7 (Q g)Q6 (Q f) Q5 (Q i) Q4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 7B9331 21 20 19 18 17 16 15
ENSYNC LOOP INA+ INA- INB(INB+) SI(INB- ) ECL TTL
FRAMER
DATA
SHIFTER DECODER REGISTER
STATUS REFCLK MODE BISTEN
INB(INB+) SI(INB- ) MODE REFCLK VCCQ STATUS CLK0 VCCQ GND SC/D(Qa) Q0 (Q b) Q1 (Q c) Q2 (Q d) Q3 (Q e)
B9331-2
CLOCK SYNC
DECODER
PLCC Top View
BISTEN LOOP INA+ INA- INB (INB+) SI (INB-) MODE
TEST LOGIC
OUTPUT REGISTER
CLK0
SYNC
Q0- 7 (Qb - h)
RVS(Q j) SC/D (Qa)
B9331-1
ENSYNC GND SYNC GND VCCN RVS(Qj) (Qh) Q7
4 3 2 1 28 2726 25 5 24 6 23 7 7B9331 22 8 21 9 20 10 111213 14 15 16 171819
REFCLK VCCQ STATUS CLK0 VCCQ GND SC/D (Qa)
B9331-3
HOTLink is a trademark of Cypress Semiconductor Corporation. ESCON is a registered trademark of IBM.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
(Q g) Q 6 (Q f) Q5 (Q i) Q 4 (Q e) Q 3 (Q d) Q 2 (Q c) Q 1 (Q b) Q 0
*
408-943-2600 April 1994
PRELIMINARY
CY7B9331 HOTLink Receiver Pin Description Name Q0 -7 (Qb - h) SC/D(Qa) I/O TTL Out TTL Out Description
CY7B9331
Q0-7 Parallel Data Output. Q0-7 contain the most recently received data. These outputs change synchronously with Clk0. When MODE is HIGH, Q 0, 1, ...7 become Qb, c,...h respectively. Special Character/Data Select. SC/D indicates the context of received data. HIGH indicates a Control (Special Character) code, LOW indicates a Data character. When MODE is HIGH, SC/D acts as Q a output. Received Violation Symbol. A HIGH on RVS indicates that a code rule violation has been detected in the received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW on RVS indicates correct operation of the transmitter, receiver, and link on a byte-by-byte basis. When MODE is HIGH, RVS acts as Q j output. In Encoded mode, SYNC asserted HIGH indicates that new data has been received and is ready to be delivered. SYNC asserted LOW shows that the received data is the Null character (normally inserted by the transmitter as a pad between data inputs). In Bypass mode, SYNC stays LOW except to indicate a K28.5 character when the framer is enabled (ENSYNC HIGH). In BIST mode, SYNC will remain HIGH for all but the last byte of a test loop and will pulse LOW one byte time per BIST loop. Recovered Byte Clock. This byte rate clock output is phase and frequency aligned to the incoming serial data stream. SYNC, Q0-7, SC/D, and RVS all switch synchronously with the rising edge of this output. Serial Data Input Select. This ECL 100K (+5V referenced) input selects INB or INA as the active data input. If LOOP is HIGH, INB is connected to the shifter and signals connected to INB will be decoded. If LOOP is LOW INA is selected. Serial Data Input A. The differential signal at the receiver end of the communication link may be connected to the differential input pairs INA or INB. Either the INA pair or the INB pair can be used as the main data input and the other can be used as a loopback channel or as an alternative data input selected by the state of LOOP. Serial Data Input B. This pin is either a single-ended ECL data receiver (INB) or half of the INB of the differential pair. If STATUS is wired to VCC, then INB can be used as differential line receiver interchangeably with INA. If STATUS is normally connected and loaded, INB becomes a single-ended ECL 100K (+5V referenced) serial data input. INB is used as the test clock while in Test mode. Status Input. This pin is either a single-ended ECL status monitor input (SI) or half of the INB of the differential pair. If STATUS is wired to VCC, then INB can be used as differential line receiver interchangeably with INA. If STATUS is normally connected and loaded, SI becomes a single-ended ECL 100K (+5V referenced) status monitor input. Status Out. Status is the inverted TTL-translated output of SI. It is typically used to translate the Carrier Detect output from a fiberoptic receiver. When this pin is normally connected and loaded (without any external pull-up resistor), STATUS will assume the negative logical level of SI and INB will become a single-ended ECL serial data input. If the status monitor translation is not desired, then STATUS may be wired to VCC and the INB pair may be used as a differential serial data input. Reframe Enable. ENSYNC controls the Framer logic in the receiver. When ENSYNC is held HIGH, each SYNC (K28.5) symbol detected in the shifter will frame the data that follows. When ENSYNC is held LOW, the reframing logic is disabled. The incoming data stream is then continuously deserialized and decoded using byte boundaries set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC characters to reframe the data erroneously. Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL. REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream. REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within CKW0.1%). Decoder Mode Select. The level on the MODE pin determines the decoding method to be used. When wired to GND (Encoded Mode), MODE selects 8B/10B decoding. When wired to VCC (Bypass MODE), registered shifter contents bypass the decoder and are sent to Q a-j directly. When left floating (internal resistors hold the MODE pin at VCC/2) the internal bit clock generator is disabled and INB becomes the bit rate test clock to be used for factory test. In typical applications, MODE is wired to VCC or GND.
RVS (Qj)
TTL Out
SYNC
TTL Out
CLK0
TTL Out
LOOP
ECL in
INA
Diff In
INB (INB+)
ECL in (Diff In )
SI (INB-)
ECL in (Diff In)
STATUS
TTL Out
ENSYNC
TTL In
REFCLK
TTL In
MODE
3-Level In
2
PRELIMINARY
CY7B9331 HOTLink Receiver Pin Description (continued) Name BISTEN I/O TTL In Description
CY7B9331
Built-In Self-Test Enable. When BISTEN is LOW the receiver awaits a D0.0 (sent once per BIST loop) character and begins a continuous test sequence that tests the functionality of the transmitter, the receiver, and the link connecting them. In BIST mode the status of the test can be monitored with Sync and RVS outputs. In normal use BISTEN is held HIGH or wired to VCC. Power for output drivers. Power for internal circuitry. Ground Output Current into TTL Outputs (LOW) ..................... 30 mA Output Current into ECL outputs (HIGH) .....................-50 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
VCCN VCCQ GND
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................... -65C to +150C Ambient Temperature with Power Applied .................................................. -55C to +125C Supply Voltage to Ground Potential..................-0.5V to +7.0V DC Input Voltage .................................................-0.5V to +7.0V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics
Parameter Description Test Conditions IOH = - 2 mA IOL = 4 mA VOUT =0V[1] -15 2.0 -0.5 VIN = VCC VIN = 0.0V VCC-1.165 2.0 VIN = VIHE Max. VIN = VILL Min. +0.5 -10 Min. Max. Unit Receiver TTL-Compatible Pins: Q0-7, SC/D, RVS, Sync, Clk0, REFCLK, EnSync, BISTEN, Status VOHT VOLT IOST VIHT VILT IIHT IILT VIHE VILE IIHE[2] IILE[2] VDIFF VIHH VILL IIHH IILL
[3]
Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
2.4 0.45 -90 VCC 0.8 +10 -500
V V mA V V A A
Receiver ECL-Compatible Input Pins: Loop, SI, INB Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current VCC VCC-1.475 +500 V V A A
Differential Line Receiver Input Pins: INA+, INA-, INB+, INB- Input Differential Voltage |(IN+) - (IN- )| Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current VIN = VIHH Max. VIN = VILL Min. -200 2.0 750 50 1200 VCC mV V V A A
Notes: 1. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 2. Applies to Loop only. 3. Input currents are always positive at all voltages above VCC/2.
3
PRELIMINARY
Electrical Characteristics (continued)
Parameter Miscellaneous ICCR[4] Receiver Power Supply Current Freq. = Max Description Test Conditions Min. Typ. 130
CY7B9331
Max. Max. 150
Unit
mA
Capacitance[5]
Parameter C IN Description Input Capacitance Test Conditions TA = 25C, f0 = 1 MHz, VCC = 5.0V Max. 10 Unit pF
Notes: 4. Maximum ICCR is measured with VCC=Max., RF=LOW, and outputs unloaded. Typical ICCR is measured with VCC=5.0V, TA=25C, RF=LOW, BISTEN=LOW, and outputs unloaded. 5. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V OUTPUT R1=910 R2=510 CL < 30 pF (Includesfixtureand probecapacitance) R1
R2
[6]
(a) TTL AC Test Load
3.0V 3.0V 2.0V GND < 1 ns 1.0V 2.0V 1.0V < 1 ns
B9331-4
VIHE 80% VILE 20%
VIHE 80% 20% VILE < 1 ns
B9331-5
< 1 ns
(c) TTL Input Test Waveform
(d) ECL InputTest Waveform
Receiver Switching Characteristics Over the Operating Range
7B9331 Parameter tCKR tB tCPRH tCPRL tA tROH tCKX tCPXH tCPXL tDS
[8]
Description Read Clock Period (No Serial Data Input), REFCLK as Reference Bit Time
[7]
Min. -1 3.03 5tB-3 5tB-3 2tB-3 2tB-3
[11]
Max. +1 6.25
Unit % ns ns ns
Read Clock Pulse HIGH Read Clock Pulse LOW Data Access Time Data Hold Time
[9, 10] [9,10 ]
2tB+4 +0.1
ns ns % ns ns
REFCLK Clock Period Referenced to CKW of Transmitter (CY7B923) REFCLK Clock Pulse HIGH REFCLK Clock Pulse LOW Propagation Delay SI to Status (note ECL and TTL thresholds)
[12]
-0.1 6.5 6.5
20
ns
4
PRELIMINARY
Switching Waveforms for the CY7B9331 HOTLink Receiver
tCKR tCPRH tCPRL CLK0
CY7B9331
SYNC tA tROH
Q0 - Q7, SC/D,RVS
B9331-6
tCKX tCPXL tCPXH
REFCLK
[11]
B9331-7
SI
Vbb tDS
STATUS
NOTE
[12]
1.5V
B9331-8
Notes: 6. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 7. The period of tCKR will match the period of the transmitter (CY7B923) CKW when the receiver is receiving serial data. When data is interrupted, Clk0 may drift to one of the range limits above. 8. Receiver tB is calculated as tClk0 /10 if no data is being received, or tCKW/10 if data is being received. 9. Data includes Q0-7 , SC/D, RVS, and Sync. 10. tA and tROH specifications are only valid if all outputs (Clk0, Sync, Q0-7, SC/D, and RVS) are loaded with similar DC and AC loads. 11. REFCLK has no phase or frequency relationship with Clk0 and only acts as a centering reference to reduce clock synchronization time. REFCLK must be within 0.1% of the transmitter CKW frequency, necessitating a 500-PPM crystal. 12. The ECL switching threshold is the midpoint between the ECL-- VOH, and VOL specification (approximately VCC -- 1.35V). The TTL switching threshold is 1.5V.
5
PRELIMINARY
Ordering Information
Ordering Code CY7B9331-JC CY7B9331-SC Document #: 38-00359 Package Name J64 S21 Package Type 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) SOIC Operating Range Commercial
CY7B9331
6
PRELIMINARY
Package Diagrams
28-Lead Plastic Leaded Chip Carrier J64
CY7B9331
28-Lead (300-Mil) Molded SOIC S21
(c) Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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